Spring 11:SMR
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Revision as of 16:01, 18 March 2011 by Gustavo Goretkin (Talk | contribs)
Progress Report 2011 03 18
This week:
- began familiarizing myself with the Altera design tool chain and Verlog
- Verilog'd a simple state machine and simulated design
- simulated design of a sine wave generator
- realized simple binary counter with LEDs on dev. board
- loaded quarter sine wave look-up table and read out sine values using LEDs and pushbuttons on the board.
- realized a sawtooth wave generator and output values to DAC on the Terasic daughter card.
Issues:
- the Terasic data conversion cards couple the single-ended in/out on the SMA connectors to the differential in/out of the ADC/DAC by a balun transformer. This means that the bandwidth of the inputs/outputs does not extend to DC. I asked on the Altera forums: http://www.alteraforum.com/forum/showthread.php?t=28443 and was directed to this post: http://www.alteraforum.com/forum/showpost.php?p=20395&postcount=10.
- Since the 3dB point is at 400kHz and since the SMR resonance frequencies are around this point (and lower for longer resonators), it might be necessary to modify the board DAC in/out to remove the DC blocking components.
Up-coming week:
- elucidate some syntax questions
- review synthesizible and unsynthesizable commands
