Spring 11:SMR

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Progress Report 2011 04 15

This week:

  • Meet with Prof's.
  • Python interface via TCP/IP with board
  • Can synthesize arbitrary frequency sine wave
  • Can sample up to 10k samples from both channels.
  • Code to fit four parameter sine wave (amplitude, frequency, vertical shift, phase) to sampled waveform
  • Code to scan frequencies and measure gain/phase offset
  • Code to simulate an LTI system given some probing sine-wave
  • Built a second-order circuit to mimic SMR

SMeRstaz: Page 249 of "Operational Amplifiers Fifth Edition -Clayton and Winder"

$ C_1=C_2=470\times10^{-12} \text{F} $

$ R_1=10638 \Omega $

$ R_2=1182 \Omega $

$ R_3=R_4=R_5=R_6=1 \text{k} \Omega $

Results in $ Q = 3 $, which is far from 100-10000 of real SMR but feedback systems (e.g. Op-Amps) enjoy oscillating.

Issues:

  • Trying to sample more than 10k samples results in data corruption.
  • Why am I getting a wonky waveform even when the circuit is supposed to be in sinusoidal steady-state?

Up-coming week:

  • Keep better documentation
  • Actually do network analysis
  • Electrical interface to SMR


Progress Report 2011 04 08

This week:

  • Met with Wasserman, Scott, Nigel, applied maths guy, et al. to discuss mass distribution estimation with SMR
  • Characterized balun transformer on DAC output. Maybe it's not necessary to modify circuit after all.
  • Decide to build on existing MRI code. Much less daunting

Progress Report 2011 03 18

This week:

  • began familiarizing myself with the Altera design tool chain and Verlog
  • Verilog'd a simple state machine and simulated design
  • simulated design of a sine wave generator
  • realized simple binary counter with LEDs on dev. board
  • loaded quarter sine wave look-up table and read out sine values using LEDs and pushbuttons on the board.
  • realized a sawtooth wave generator and output values to DAC on the Terasic daughter card.

Issues:

  • the Terasic data conversion cards couple the single-ended in/out on the SMA connectors to the differential in/out of the ADC/DAC by a balun transformer. This means that the bandwidth of the inputs/outputs does not extend to DC. I asked on the Altera forums: http://www.alteraforum.com/forum/showthread.php?t=28443 and was directed to this post: http://www.alteraforum.com/forum/showpost.php?p=20395&postcount=10.
  • Since the 3dB point is at 400kHz and since the SMR resonance frequencies are around this point (and lower for longer resonators), it might be necessary to modify the board DAC in/out to remove the DC blocking components.

Up-coming week:

  • elucidate some syntax questions
  • review synthesizible and unsynthesizable commands